The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
An error correction code (“ECC”) decoder may be used to decode encoded data, which may include one or more “codewords,” on a channel. For example, a memory controller may use an ECC decoder to handle bit errors and recover data associated with an ECC codeword stored in a die of non-volatile memory (“NVM”). As another example, an ECC decoder may be used to handle bit errors and recover data associated with encoded incoming data on a wired or wireless communication channel.
An iterative decoder such as a non-binary low-density parity-check (“LDPC”) decoder may process a codeword multiple times, with each iteration bringing the codeword closer to the original data. In one form of iterative decoding called “extended min-sum,” symbols and associated probabilities that the symbols are correct may be passed between variable nodes and check nodes corresponding to relationships between the variable nodes. A forward-backward algorithm may be used to break up the computation involved with a single check node into computation involving multiple elementary check nodes.